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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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Advance Information
MCM321024
PIN ASSIGNMENT TOP VIEW 72 LEAD SIMM -- CASE TBD
NC PD3 PD0 DQ0 DQ1 DQ2 DQ3 VCC A7 A8 A9 DQ4 DQ5 DQ6 DQ7 W A14 E1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 NC PD2 VSS PD1 DQ8 DQ9 DQ10 DQ11 A0 A1 A2 DQ12 DQ13 DQ14 DQ15 VSS A15 E2
1M x 32 Bit Fast Static RAM Module
The MCM321024 is an 32M bit static random access memory module organized as 1,048,576 words of 32 bits. The module is a 72-lead single in-line memory module (SIMM) consisting of eight MCM6249 fast static RAMs packaged in 32-lead SOJ packages and mounted on a printed circuit board along with sixteen decoupling capacitors. The MCM6249 is a high performance CMOS fast static RAM organized as 1,048,576 words of 4 bits. Static design eliminates the need for external clocks or timing strobes, while CMOS circuitry reduces power consumption and provides for greater reliability. The MCM321024 is equipped with output enable (G) and four separate byte enable (E1 - E4) inputs, allowing for greater system flexibility. The G input, when high, will force the outputs to high impedance. Ex high will do the same for byte x. PD0 - PD3 are reserved for density identification. PD0 and PD2 are connected to ground. These pins can be used to identify the density of the memory module. Single 5 V 10% Power Supply Fast Access Time: 20/25 ns Three-State Outputs Fully TTL Compatible JEDEC Standard Pinout Power Requirement: 1520/1400 mA Maximum, Active AC High Board Density SIMM Package Byte Operation: Four Separate Chip Enables, One for Each Byte (Eight Bits) High Quality Six-Layer FR4 PWB with Separate Internal Power and Ground Planes * Incorporates Motorola's State-of-the-Art Fast Static RAMs * * * * * * * * *
E3 A16 VSS DQ16 DQ17 DQ18 DQ19 A10 A11 A12 A13 DQ20 DQ21
38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71
E4 A17 G DQ24 DQ25 DQ26 DQ27 A3 A4 A5 VCC A6 DQ28 DQ29 DQ30 DQ31 A18 NC
PIN NAMES
A0 - A19 . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Inputs W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Enable G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Enable E1 - E4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Byte Enables DQ0 - DQ31 . . . . . . . . . . . . . . . . . . . . . . Data Input/Output VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . + 5 V Power Supply VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground PD0 - PD3 . . . . . . . . . . . . . . . . . . . . . . . . Package Density NC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . No Connect For proper operation of the device, VSS must be connected to ground.
DQ22 DQ23 VSS A19 NC
This document contains information on a new product. Specifications and information herein are subject to change without notice. REV 1 11/15/96
(c) Motorola, Inc. 1996 MOTOROLA FAST SRAM
MCM321024 1
FUNCTIONAL BLOCK DIAGRAM 1M x 32 MEMORY MODULE
4 DQ0 - DQ3 A0 - A19 E W G E1 4 E3 4 DQ0 - DQ3 A0 - A19 E W G DQ20 - DQ23 DQ0 - DQ3 A0 - A19 E W G 4
DQ0 - DQ3
DQ16 - DQ19
DQ0 - DQ3 A0 - A19 E W G
DQ4 - DQ7
DQ8 - DQ11
4
DQ0 - DQ3 A0 - A19 E W G
DQ24 - DQ27
4
DQ0 - DQ3 A0 - A19 E W G
E2 4 DQ12 - DQ15 DQ0 - DQ3 A0 - A19 E W G
E4 4
DQ28 - DQ31
DQ0 - DQ3 A0 - A19 E W G
W G VCC VSS A0 - A19 PD0, PD2 PD1, PD3 - OPEN
MCM321024 2
MOTOROLA FAST SRAM
TRUTH TABLE
Ex H L L L G X H L X W X H H L Mode Not Selected Read Read Write VCC Current ISB1 or ISB2 ICCA ICCA ICCA Output High-Z High-Z Dout Din Cycle -- -- Read Cycle Write Cycle
ABSOLUTE MAXIMUM RATINGS (Voltages referenced to VSS = 0 V)
Rating Power Supply Voltage Voltage Relative to VSS Output Current (per I/O) Power Dissipation Temperature Under Bias Operating Temperature Storage Temperatrue Symbol VCC Vin, Vout Iout PD Tbias TA Tstg Value - 0.5 to 7.0 - 0.5 to VCC + 0.5 30 8.0 - 10 to + 85 0 to + 70 - 25 to + 125 Unit V V mA W C C C The devices on this module contain circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high impedance circuits. These CMOS memory circuits have been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The module is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 10%, TA = 0 to + 70C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (Voltages Referenced to VSS = 0 V)
Parameter Supply Voltage (Operating Voltage Range) Input High Voltage Input Low Voltage * VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2 V ac (pulse width 20 ns) ** VIL (min) = - 3.0 V ac (pulse width 20 ns) Symbol VCC VIH VIL Min 4.5 2.2 - 0.5** Typ 5.0 -- -- Max 5.5 VCC + 0.3* 0.8 Unit V V V
DC CHARACTERISTICS
Parameter Input Leakage Current (All Inputs, Vin = 0 to VCC) Output Leakage Current (G, Ex = VIH, Vout = 0 to VCC) AC Active Supply Current (G, Ex = VIL, Iout = 0 mA, MCM321024-20: tAVAV = 20 ns Cycle time tAVAV min) MCM321024-25: tAVAV = 25 ns AC Standby Current (Ex = VIH, Cycle time tAVAV min) CMOS Standby Current (Ex VCC - 0.2 V, All Inputs VCC - 0.2 V or 0.2 V) Output Low Voltage (IOL = + 8.0 mA) Output High Voltage (IOH = - 4.0 mA) NOTE: Good decoupling of the local power supply should always be used. Symbol Ilkg(I) Ilkg(O) ICCA ISB1 ISB2 VOL VOH Min -- -- -- -- -- -- -- 2.4 Typ -- -- 1440 1320 400 80 -- -- Max 8 8 1520 1400 480 120 0.4 -- Unit A A mA mA mA V V
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25C, Periodically Sampled Rather Than 100% Tested)
Characteristic Input Capacitance (All pins except DQ0 - DQ31, W, G, and E1 - E4) E1 - E4 W, G (DQ0 - DQ31) Symbol Cin Typ 32 10 40 8 Max 48 14 64 9 Unit pF
Input/Output Capacitance
Cout
pF
MOTOROLA FAST SRAM
MCM321024 3
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 10%, TA = 0 to + 70C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Output Load . . . . . . . . . . . . . See Figure 1a Unless Otherwise Noted Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns
READ CYCLE TIMING (See Notes 1 and 2)
MCM321024-20 Parameter Read Cycle Time Address Access Time Enable Access Time Output Enable Access Time Output Hold from Address Change Enable Low to Output Active Output Enable to Output Active Enable High to Output High-Z Output Enable High to Output High-Z Power Up Time Power Down Time Symbol tAVAV tAVQV tELQV tGLQV tAXQX tELQX tGLQX tEHQZ tGHQZ tELICCH tEHICCL Min 20 -- -- -- 5 5 0 0 0 0 -- Max -- 20 20 7 -- -- -- 9 9 -- 20 MCM321024-25 Min 25 -- -- -- 5 5 0 0 0 0 -- Max -- 25 25 9 -- -- -- 10 10 -- 25 Unit ns ns ns ns ns ns ns ns ns ns ns 4,5,6 4,5,6 4,5,6 4,5,6 Notes 3
NOTES: 1. W is high for read cycle. 2. E1 - E4 are represented by E in these timing specifications, any combination of Exs may be asserted. 3. All read cycle timing is referenced from the last valid address to the first transitioning address. 4. At any given voltage and temperature, tEHQZ max is less than tELQX min, and tGHQZ max is less than tGLQX min, both for a given device and from device to device. 5. Transition is measured 500 mV from steady-state voltage with load of Figure 1b. 6. This parameter is sampled and not 100% tested. 7. Device is continuously selected (E = VIL, G = VIL). See Read Cycle 1.
TIMING LIMITS
+5V RL = 50 OUTPUT Z0 = 50 VL = 1.5 V OUTPUT 255 5 pF 480 The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time. On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time.
(a)
(b) Figure 1. Test Loads
MCM321024 4
MOTOROLA FAST SRAM
READ CYCLE 1 (See Note 7 Above)
tAVAV A (ADDRESS) tAXQX Q (DATA OUT) PREVIOUS DATA VALID tAVQV DATA VALID
READ CYCLE 2 (See Note)
tAVAV A (ADDRESS) tELQV Ex (BYTE ENABLE) tELQX G (OUTPUT ENABLE) tGLQV tGLQX Q (DATA OUT) tAVQV VCC SUPPLY CURRENT ICC ISB tELICCH DATA VALID tEHICCL tGHQZ tEHQZ
NOTE: Addresses valid prior to or coincident with E going low.
MOTOROLA FAST SRAM
MCM321024 5
WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
MCM321024-20 Parameter Write Cycle Time Address Setup Time Address Valid to End of Write Write Pulse Width Data Valid to End of Write Data Hold Time Write Low to Data High-Z Write High to Output Active Write Recovery Time Symbol tAVAV tAVWL tAVWH tWLWH, tWLEH tDVWH tWHDX tWLQZ tWHQX tWHAX Min 20 0 15 15 10 0 0 5 0 Max -- -- -- -- -- -- 9 -- -- MCM321024-25 Min 25 0 17 17 10 0 0 5 0 Max -- -- -- -- -- -- 10 -- -- Unit ns ns ns ns ns ns ns ns ns 4,5,6 4,5,6 Notes 3
NOTES: 1. A write occurs during the overlap of E low and W low. 2. E1 - E4 are represented by E in these timing specifications, any combination of Exs may be asserted. G is a don`t care when W is low. 3. All write cycle timing is referenced from the last valid address to the first transitioning address. 4. Transition is measured 500 mV from steady-state voltage with load of Figure 1b. 5. This parameter is sampled and not 100% tested. 6. At any given voltage and temperature, tWLQZ max is less than tWHQX min both for a given device and from device to device.
WRITE CYCLE 1
tAVAV A (ADDRESS) tAVWH Ex (BYTE ENABLE) tWLWH W (WRITE ENABLE) tAVWL D (DATA IN) tWLQZ Q (DATA OUT) HIGH-Z HIGH-Z tDVWH DATA VALID tWHQX tWHDX tWHAX
MCM321024 6
MOTOROLA FAST SRAM
WRITE CYCLE 2 (E Controlled, See Notes 1 and 2)
MCM321024-20 Parameter Write Cycle Time Address Setup Time Address Valid to End of Write Enable to End of Write Enable to End of Write Write Pulse Width Data Valid to End of Write Data Hold Time Write Recovery Time Symbol tAVAV tAVEL tAVEH tELEH tELWH tWLEH tDVEH tEHDX tEHAX Min 20 0 15 15 15 15 10 0 0 Max -- -- -- -- -- -- -- -- -- MCM321024-25 Min 25 0 17 17 17 17 10 0 0 Max -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns 4,5 Notes 3
NOTES: 1. A write occurs during the overlap of E low and W low. 2. E1 - E4 are represented by E in these timing specifications, any combination of Exs may be asserted. G is a don't care when W is low. 3. All write cycle timing is referenced from the last valid address to the first transitioning address. 4. If E goes low coincident with or after W goes low, the output will remain in a high impedance condition. 5. If E goes high coincident with or before W goes high, the output will remain in a high impedance condition.
WRITE CYCLE 2
tAVAV A (ADDRESS) tAVEH Ex (BYTE ENABLE) tAVEL W (WRITE ENABLE) tWLEH D (DATA IN) tDVEH DATA VALID tEHDX Q (DATA OUT) HIGH-Z tELEH tELWH tEHAX
ORDERING INFORMATION
(Order by Full Part Number) MCM 321024 XX XX
Motorola Memory Prefix Part Number
Speed (20 = 20 ns, 25 = 25 ns) Package (SG = Gold Pad SIMM)
Full Part Numbers -- MCM321024SG20
MCM321024SG25
MOTOROLA FAST SRAM
MCM321024 7
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MCM321024 8
MCM321024/D MOTOROLA FAST SRAM

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